Sunday, July 8, 2012

CS9050-ROUTERS AND NETWORK PROCESSORS-B.E -CSE-COMPUTER SCIENCE AND ENGINEERING SEVENTH-VII SEMESTER 2008 REGULATION ANNA UNIVERSITY SYLLABUS



CSE Computer Science And Engineering VII-Seventh Semester Syllabus 2008 Regulation Anna University


AIM:
To  understanthe  internals  of  a  router  anget  an  experience  of  designing  such systems.

OBJECTIVES:
·    To learn the functions of a router, and its architecture.
·    To learn about Network processors their architecture, programming issues, and design issues.

UNIT I           ROUTING IN IP NETWORKS                                                                     9
Static Routes Dynamic Routes RIP v1, RIP v2 IGRP EIGRP OSPF
Integrated IS-IS IP Traffic engineering Traffic, Stochasticity, Delay and Utilization  Application view – Architecture Framework EGP, BGP routing.

UNIT II          ROUTER ARCHITECTURE                                                                        9
Function of Router Types – Elements Packet flow Packet Processing - Algorithms And Data Structures (packet buffer allocation, etc) - Packet processing functions (Bridge Algorithm, Table Lookup And Hashing, etc)- Protocol Software (threads, Interrupts, etc) - Hardware Architectures For Protocol Processing - Classification And Forwarding Switching Fabrics.

UNIT III         NETWORK PROCESSORS                                                                        9
Scalability With Parallelism And Pipelining    - Complexity Of Network Processor Design (packet processing, ingress & egress  processing, Macroscopic Data Pipelining And Heterogeneity    etc) - Network Processor Architectures : architectural variety, Primary architectural characteristics, Packet Flow, Clock Rates, software architecture, Assigning Functionality To The Processor Hierarchy.

UNIT IV        NP ARCHITECTURES                                                                                9
Issues In Scaling A Network Processor (processing hierarchy and scaling) examples of commercial Network Processors : Multi-Chip Pipeline, Augmented RISC Processor, Embedded Processor Plus Coprocessors, etc. - Design Tradeoffs and consequences (Programmability Vs. Processing Speed , speed vs functionality. etc).

UNIT V         CASE STUDY NP ARCHITECTURE AND PROGRAMMING                 9
Intel  NP  -  MultithreadeArchitecture  Overview  –  Basic  Features,  External Connections, Internal components Embedded RISC processor (instruction set, internal peripheral unit, User And Kernel Mode Operation) -Packet Processor Hardware (microsequencing, instruction set, etc) memory interfaces – system and control interface components Bus interface -Software Development Kit IXP instruction set – MicroEngine Programming - thread synchronization developing sample applications.





TEXT BOOKS:

TOTAL: 45 PERIODS

1.  Douglas  E.  Comer  ”Network  System  Design  using  Network  Processors” Prentice Hall, 2006.
2.  Deepankar Medhi, Karthikeyan Ramasamy, “Network Routing : Algorithms, Protocols, and Architecture, Elsevier, 2007.
REFERENCES:
1. Patrick Crowley, M A Franklin, H Hadimioglu, PZ Onufryk, Network
Processor Design, Issues and Practices Vol - I, Morgan Kauffman, 2002.


2. http://www.npforum.org/ 3. http://www.intel.com/design/network/products/npfamily/

7/08/2012 02:43:00 AM

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